JPH0549131B2 - - Google Patents

Info

Publication number
JPH0549131B2
JPH0549131B2 JP62300917A JP30091787A JPH0549131B2 JP H0549131 B2 JPH0549131 B2 JP H0549131B2 JP 62300917 A JP62300917 A JP 62300917A JP 30091787 A JP30091787 A JP 30091787A JP H0549131 B2 JPH0549131 B2 JP H0549131B2
Authority
JP
Japan
Prior art keywords
output
input
drive
circuit
address decoder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62300917A
Other languages
English (en)
Japanese (ja)
Other versions
JPH01141415A (ja
Inventor
Minoru Kikuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP62300917A priority Critical patent/JPH01141415A/ja
Publication of JPH01141415A publication Critical patent/JPH01141415A/ja
Publication of JPH0549131B2 publication Critical patent/JPH0549131B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1731—Optimisation thereof
    • H03K19/1732—Optimisation thereof by limitation or reduction of the pin/gate ratio

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Electronic Switches (AREA)
  • Logic Circuits (AREA)
JP62300917A 1987-11-27 1987-11-27 出力駆動回路 Granted JPH01141415A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62300917A JPH01141415A (ja) 1987-11-27 1987-11-27 出力駆動回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62300917A JPH01141415A (ja) 1987-11-27 1987-11-27 出力駆動回路

Publications (2)

Publication Number Publication Date
JPH01141415A JPH01141415A (ja) 1989-06-02
JPH0549131B2 true JPH0549131B2 (en]) 1993-07-23

Family

ID=17890686

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62300917A Granted JPH01141415A (ja) 1987-11-27 1987-11-27 出力駆動回路

Country Status (1)

Country Link
JP (1) JPH01141415A (en])

Also Published As

Publication number Publication date
JPH01141415A (ja) 1989-06-02

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